1. Technical Field
The present invention relates in general to data processing and, in particular, to efficient data transfer in a data processing system. Still more particularly, the present invention relates to a write pipeline utilized to sequentially accumulate a plurality of data granules for transfer in association with a single address.
2. Description of the Related Art
It has been recognized in the art that the overall performance of conventional data processing systems depends not only upon the individual performance of the constituent components of the data processing system, but also upon the efficiency of data transfer between the components. For example, in a conventional data processing system including a processor and a memory system, many strategies have been proposed and implemented in order to improve the efficiency of data transfer between the processor and the memory system. One such strategy is referred to as store gathering.
Store gathering typically refers to a strategy of data transfer from the processor to the memory system in which the processor is equipped with a store gathering buffer that collects data associated with a number of smaller (e.g., two byte) store operations associated with multiple memory addresses in a defined address range and then outputs all of the collected data in a single larger (e.g., eight byte) store operation. Conventional store gathering has the advantage of reducing the number of data tenures utilized to store a given number of data bytes by utilizing the full bandwidth of the data portion of the interconnect. Store gathering buffers tend, however, to be quite complex to implement in that the store gathering buffer must be able to handle operating scenarios in which addresses of incoming store operations partially or fully overlap, too few store operations in a given address range are received to utilize the full bandwidth of the data interconnect, buffer full conditions, etc. Because of this complexity, store gathering buffers are expensive to implement and consume a large amount of chip area.
Another characteristic of conventional store gathering buffers is that they do not preserve the ordering of incoming store operations. That is, after the smaller store operations are gathered in the buffer and transferred to a memory system (or other recipient), the order in which the smaller store operations were received by the store gathering buffer cannot be determined by the recipient from the larger gathered store operation. Thus, conventional store gathering buffers cannot be employed in data processing applications in which data transfer is order-sensitive.
The shortcomings and disadvantages of conventional store gathering buffers described above are addressed and overcome by the write pipeline and method of data transfer introduced by the present invention.
According to the present invention, an exemplary data processing system may include an interconnect and first and second components coupled to the interconnect for data transfer therebetween. The first component contains a write pipeline that includes an address register and a queue having storage locations for a plurality of data granules. In response to receipt of a plurality of data granules that are each associated with a single address specified by the address register, the queue loads the plurality of data granules into sequential storage locations in order of receipt. Upon the queue being filled with a predetermined number of data granules, the queue outputs, to the second component via the interconnect, the predetermined number of data granules at least two at a time according to the order of receipt. In a preferred embodiment, the queue is implemented as a circular first-in, first-out (FIFO) queue. Thus, data transfer efficiency is enhanced utilizing a simple queue structure while maintaining the input ordering of the data granules.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.